The present invention relates mainly to a method and a circuit arrangement for controlling insertion, storage, and retrieval of digital information in a memory so that not only is the digital information correctly stored but also correctly read out of the memory, before the read information, in the form of a number of coordinated bit positions, is used to control one or several functions.
The method and circuit arrangement according to the invention is more specifically intended to control retrieval of information, coordinated into data packets or data cells, from a memory so that the information read out of a memory and corresponding to a specific address is correct.
This application claims priority from Swedish patent application Serial No. 94 01318-2 filed on Apr. 19, 1994, which is incorporated here by reference.
Telecommunication systems that use data packets for required exchange of signals are previously known in various designs. For the required exchange of signals, one such system uses a number of bit positions, coordinated into structured sets of bits, that in turn are structured and coordinated into data packets. Within a known ATM-system such structured data packets are called "data cells", but in the following, the term "data packets" will be used more generally.
Data packets (data cells) of this kind, especially standardized data packets, are characterized such that certain bit positions are coordinated into sets of bits representing an addressing or address-related field (designated "Header") and including, among other things, a virtual address, also called channel number. Other bit positions are structured into a set of bits representing a user-related-information-carrying or information-content-related field (designated "Payload") and including data information from the user.
It is also previously known that, in order to realize certain hardware functions within a switching unit in an optimal way, only switch internally usable data packets or data cells are used. In addition to bit positions and sets of bits in a standardized data packet, further bit positions structured as a "label" are used. Label fields or label-related bit positions and sets of bits can be added to an incoming data packet, and the label field is used within the switching unit in order to direct the data packet to an out going link with the guidance of the bit positions and their digital values.
It is also previously known to use various kinds of memories within a telecommunication system and switching unit. Memories that store the digital information during a relatively short time are often designated buffer memories.
For a person skilled in the art, it is obvious that there is a great need for buffer memories and queue management of data packets with various bit positions and structures. A first flow of digital information, in the form of data packets, varies and has a mean flow rate somewhat lower than a second flow of digital information, meaning that a flow of information in to a buffer memory can, over short periods of time, be higher or lower than a corresponding flow out of the same memory. The mean flow into the memory is selected to be somewhat lower than the mean flow out of the memory.
There are also previously known various methods and devices used to ensure that digital information inserted into and stored within a memory is correctly readable out of the memory. A very well known method for this purpose is to let the digital information include bit positions, structured with a selected number of information-carrying bit positions, a selected number of address-carrying bit positions and/or a selected number of control-sum-carrying bit positions. The control-sum-carrying bit positions represent a selected evaluation of the selected number of information-carrying bit positions, through, for instance, a calculation or evaluation of parity bits or a "check sum" formed through a selected polynomial. The control-sum-carrying bit positions carry a "control sum", representing either formed parity bits or a calculated check sum, regardless of the selected control method.
A parity control and a device for a chip-related memory are previously known through the European patent publication EP A2 0 449 052 which describes a parity control of address signals. The parity is controlled before a digitized word is stored within a memory. An integrated circuit with an input register to receive a number of addressing bits, a set of memories to store information in a number of addressable storage positions, a control unit to evaluate at least one of the addressable storage positions corresponding to the address bits and a unit to control the parity of the address bits. A memory circuit controls parity control before a digitized word is stored in the memory circuit.
European patent publication EP A10 554 964 illustrates a storage and transfer circuit and a method to maintain the integrity of the data during a storage sequence. A calculation of a first partial control sum from a selected data field within a frame and a unit for storage of the control sum is described. A unit is oriented in a parallel relation to a series generating device, in order to evaluate a second partial control sum comprising only the data field. A unit compares the first and second partial control sum, and units that can be activated at a comparison change the new calculated control-sum as soon as the two partial control sums are not identical, before a series conversion is completed.
The construction of an ATM-cell, with cyclic redundancy check (CRC) bits at the end of the cell, is described in the European patent publication EP A1 0 531 599. Such ATM-cells can be used advantageously in accordance with the present invention. The European patent publication EP A1 0 545 575 also presents a data packet with an ending error controlling field.
A memory system in which it is possible to evaluate a data error is shown and described in the European patent publication EP A2 0 084 460. Addressing errors are discovered by forming parity information over the address and inserting it into control fields belonging to every memory position. A signal, indicating the present status of the function in the memory module, is generated in every memory module and transferred to a data processing system to be compared with a status of a signal indicating function in order to ensure that the memory module and the memory control in the process receive the same order.
U.S. Pat. No. 4,872,172 shows a circuit where a data bus transfers a data word. The data word includes eight bits with data information and one parity bit and is stored within a buffer memory temporarily before it is transferred on to be processed in a logical circuit. Every data word (data and parity bit) that is stored in the buffer register is processed in a parity calculating circuit. A parity control circuit generates a signal representing a parity error if the parity following the data is not correct. The data word and the parity bit, that have been transferred to an outgoing bus, are transferred back to another parity controlling circuit which generates an error signal for the bus when a parity error is discovered.
IBM Technical Disclosure Bulletin, vol. 24, no. 1B, p. 794 (June 1981), describes a method of ensuring that information stored within a memory is correctly readable. A parity bit, belonging to a data byte, is generated for every data byte or word comprising a number of bit positions. The value of a parity bit is determined by the number of bits with the value "1" in both the data word and the addressing value in the address register of the memory. A further parity bit is generated at the readout of the data word from the memory, and this is calculated taking the number of 1-bit positions or the number of 1-bits in both the data word and the address initiating the readout into consideration. This further parity bit is thereafter compared with the previously stored parity bit and an error signal is generated if there is a difference.
U.S. Pat. No. 4,809,278 describes a system for ensuring that information stored in a memory is correctly readable. Parity bits are generated for every word that is stored in an addressed position. The number of parity bits can be selected to be the same as the number of input connections of each storage chip used in the storage structure. A first and a second set of Exclusive-Or gates generate a first and second set of parity data for every read-write cycle addressing the same memory position. A help-memory for parity bits receives the first set of parity data for storage in positions corresponding to similar positions in each memory chip so that the same address data will read the first set of bits of parity data corresponding to each address in the structured memory. These parity data are the input signals to a second set of Exclusive-Or gates intended to form a second set.
U.S. Pat. No. 4,692,893 shows and describes a data buffer circuit that is addressable for reading and writing by using an address with n bit positions and with an addressable read register and an addressable write register, both presenting n+1 bit positions. The extra bit position is used as a parity control. The n+1-th bit in the counters for reading and writing, respectively, is used to ensure that the respective counters are positioned at "the same turn".
European patent publication EP A1 463 210 describes a circuit intended to control the storage in and addressing of a memory. At least one write address register and at least one read address register are used. Every one of the check bits of the data word is Exclusive-Or-related with a bit in the address position. The check bits are Exclusive-Or-related with the bits of the address position once again at the readout of the word in order to regenerate their original values, so that the parity of the data word can be controlled.